DocumentCode
2982594
Title
A scalable performance 32 b microprocessor
Author
Clark, L.T. ; Hoffman, E. ; Schaecher, M. ; Biyani, M. ; Roberts, D. ; Yuyun Liao
Author_Institution
Intel Corp., Chandler, AZ, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
230
Lastpage
231
Abstract
A RISC microprocessor core in a six-layer metal 0.18 /spl mu/m CMOS process implements the ARM/sup TM/ V.5TE instruction set. The microprocessor core is 16.77 mm/sup 2/ and dissipates 450 mW at 1.3 V, 600 MHz, scaling between 55 mW, 0.7 V and 200 MHz, and 1.55 W at 1.65 V and 800 MHz.
Keywords
CMOS digital integrated circuits; instruction sets; microprocessor chips; reduced instruction set computing; 0.18 micron; 0.7 to 1.65 V; 1.3 V; 200 to 800 MHz; 32 bit; 55 mW to 1.55 W; ARM V.5TE instruction set; CMOS process; RISC microprocessor core; scalable performance; six-layer metal; Adders; CMOS logic circuits; Clocks; Decoding; Delay effects; Latches; Logic design; Logic gates; Microprocessors; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912616
Filename
912616
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