New development in CVD tungsten technology for multilevel interconnection

A newly developed low-temperature silane-reduced selective tungsten deposition process is described, which is suitable for applications in VLSI multilevel interconnection. The most important advances in the selective deposition process are the lowered deposition temperature and increased deposition rate. With the addition of silane, the deposition temperature has been lowered to below 300°C from 450 to 550°C for the conventional two-step process involving Si reduction followed by hydrogen reduction. At the same time, the deposition rate has been increased by a factor of five to ten depending on the optical density of the exposed area. Other benefits of the low-temperature process include absence of leakage currents caused by tunneling and encroachment, and much enhanced selectivity. The frequency of cleaning the deposition system has also been reduced because of reduced deposition temperature. Significantly improved electrical properties have been obtained on various devices