Demultiplexer design for multi-edge type LDPC coded modulation

Generally, the capacity-achieving signaling design for a specific channel should consider the joint optimization of channel coding and modulation. Nevertheless, coding theorists and practitioners have recognized that a well-designed LDPC code can achieve capacity-approaching performance universally across a range of data transmission and storage channels. A pronounced example is the forward error correction scheme adopted recently by the second generation standards for digital video broadcasting (DVB), wherein the same LDPC codes are expected to be reused over satellite, terrestrial and cable channels. However, to accommodate the spectral efficiency of different channel type, the coded bits should be mapped to the modulator judiciously. The well-known BICM strategy employs a large random bit interleaver, which typically yields good performance for an arbitrary choice of constellation mapper. However, it is problematic for high-speed coding and modulation due to the large amount of memory and circuits routing required. This motivates us to impose structural simplicity on the bit interleaver configuration so that the coded bits are de-multiplexed systematically into parallel groups to feed the constellation mapper. In this paper, we focus on the design of bit demultiplexers for multi-level modulations by applying the framework of multi-edge type (MET) LDPC. Since the channel-dependence of a given code ensemble is dominated by the mutual information between the input and output of the effective channel, we propose to simplify the analysis of the decoding behavior by using a set of surrogate binary erasure channels (BEC). Simulation results indicate that the proposed bit demultiplexer surpasses the performance of the heuristic interleaving strategy specified in second generation DVB standard for terrestrial channels (DVB-T2).