• DocumentCode
    2983094
  • Title

    Effectiveness of internal vs. external SEU scrubbing mitigation strategies in a Xilinx FPGA: Design, test, and analysis

  • Author

    Berg, Melanie ; Poivey, C. ; Petrick, D. ; Espinosa, D. ; Lesea, Austin ; LaBel, K. ; Friendlich, M. ; Kim, H. ; Phan, Anthony

  • Author_Institution
    NASA Goddard Space Flight Center, Greenbelt, MD, USA
  • fYear
    2007
  • fDate
    10-14 Sept. 2007
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    A comparison of two scrubbing mitigation schemes for Xilinx field programmable gate array (FPGA) devices is presented. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Heavy ion data are then presented and analyzed.
  • Keywords
    field programmable gate arrays; logic design; logic testing; SEU scrubbing mitigation strategies; Xilinx FPGA; field programmable gate array design; heavy ion data; single event unit; Circuit faults; Clocks; Field programmable gate arrays; Logic devices; Protection; Random access memory; Read-write memory; Reconfigurable logic; Space technology; Testing; FPGA; Reconfiguration; Scrubbing; Xilinx;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on
  • Conference_Location
    Deauville
  • ISSN
    0379-6566
  • Print_ISBN
    978-1-4244-1704-9
  • Type

    conf

  • DOI
    10.1109/RADECS.2007.5205603
  • Filename
    5205603
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2983094