Modified dynamic space compression for built-in self-testing of VLSI circuits

In this paper, we propose a space compression technique for digital circuits with the objective of minimizing the storage for the circuits under test while maintaining the fault coverage information. The technique introduced is called a Modified Dynamic Space Compression method. For a circuit under test, a compaction tree is generated based on its structure. The detectable error probability was calculated by using the Boolean Difference Method. The output data modification was employed to minimize the number of faulty output data patterns which have the same compressed form as the fault-free patterns. The compressed outputs were then fed into a syndrome counter to derive the signature for the circuit. Simulations were performed on known combinational circuits and the results indicate that the loss in fault coverage caused by compression is rather small