Architecture driven layout synthesis techniques for CA-type FPGAs

Predominantly local connections in new cellular architecture FPGAs present a challenge to CAD tool developers. In this paper we discuss new methodologies for low-level synthesis of digital circuits, to cellular architecture (CA) Field Programmable Gate-Arrays (FPGA). The design representation on logic level of abstraction is created or restructured in such a way that it resembles the architecture of FPGA as close as possible. The resulting structure is therefore easy to map, and a number of logic cells used for routing L minimized. Layout synthesis methods using different design representations are discussed and compared