A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

To cope with difficult device miniaturization in the multi-gigabit era, memory cells smaller than the traditional 8F/sup 2/ folded bitline (BL) cell are needed. A 6F/sup 2/ trench capacitor folded-BL cell has been recently described. However, it needs not only additional tight-pitch layers to create a vertically folded-BL arrangement, but also a vertical transistor. The 6F/sup 2/ open-BL cell enabling a simple planar transistor is another candidate as its inherently large imbalance noise between pairs of BLs is reduced. Low-voltage, high-speed array operation is essential in the multi-gigabit era. A conventional non-over-driven sensing scheme cannot achieve a high enough speed at an array voltage below 1.6 V, because the threshold voltage (Vth) cannot be reduced <0.1 V to obtain a low enough stand-by current. Distributed over-driven sensing enables a higher speed due to reduced voltage loss caused by distributed drivers combined with meshed power lines. Consequently, compared with the conventional schemes, the sensing time for a 1.2 V array voltage necessary for the 1 Gb generation decreased by 6.9 ns and 2.0 ns. Hence, this sensing scheme is promising for array voltages below 1.0 V in multi-gigabit memory. In multi-gigabit DRAMs, redundancy for degraded cells after packaging is a major concern. To overcome this a scheme is adopted which features a stacked flash fuse composed of three series flash fuses utilizing standard CMOS transistors without any additional process steps. Thus this technology can be used to fabricate a 0.13 μm 180 mm/sup 2/ 1 Gb DRAM assembled in a 400-mil package.