A 100 MHz 2.5 GHz Direct Conversion CMOS Transceiver for SDR Applications

This paper describes a fundamentally flexible low power transceiver implemented in 90 nm CMOS. Novel circuit architectures have been implemented to overcome problems that have encumbered wideband transceivers in the past. Flexible programming allows the RFIC to process signals of multiple wireless protocols from 100 MHz - 2.5 GHz with channel bandwidths from 8 KHz to 20 MHz. At 1.8 GHz the receiver noise figure is 7 dB with IP3 of -6 dBm and voltage gain of 48 dB. The transmitter has better than 40 dB carrier suppression, 35 dB sideband suppression, and EVM of 1% at 800 MHz. The frequency synthesizer uses direct digital synthesis to achieve instantaneous frequency switching and phase noise of -123 dBc/Hz at 25 KHz offset.