• DocumentCode
    2988150
  • Title

    Improving Search Speed on Pointer-Based Large Data Structures Using a Hierarchical Clustering Copying Algorithm

  • Author

    Yasugi, Masahiro ; Yuasa, Taiichi

  • Author_Institution
    Kyoto Univ., Kyoto
  • fYear
    2007
  • fDate
    11-13 Jan. 2007
  • Firstpage
    43
  • Lastpage
    52
  • Abstract
    The increasing processor-memory performance gap makes improving the cache locality as important as the virtual memory locality. In many applications, especially in search algorithms on pointer-based large data structures, breadth-first copying algorithms increase cache misses, page faults and TLB misses. Since the depth-first copying only achieves limited locality improvement, several clustering copying algorithms have been proposed. In this paper, we propose "hierarchical clustering" which groups data objects at multiple hierarchical levels and provides better locality at both the cache and virtual memory levels of the memory hierarchy. We also propose a new copying algorithm for the hierarchical clustering, which uses multiple scan pointers and bounded workspace. Our copying algorithm almost always outperforms other algorithms; after copying, two representative microbenchmarks, employing a search tree and an array of associative lists, run approximately two (sometimes five) times faster than breadth-first copying.
  • Keywords
    cache storage; data structures; tree searching; TLB misses; breadth-first copying algorithms; cache locality; cache misses; clustering copying algorithms; data objects; depth-first copying; hierarchical clustering copying algorithm; limited locality improvement; memory hierarchy; microbenchmarks; page faults; pointer-based large data structures; processor-memory performance gap; search algorithms; search speed improvement; virtual memory levels; Clustering algorithms; Computer architecture; Data structures; Degradation; Informatics; Operating systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovative architecture for future generation high-performance processors and systems, 2007. iwia 2007. international workshop on
  • Conference_Location
    Maui, HI
  • ISSN
    1537-3223
  • Print_ISBN
    0-7695-3077-X
  • Type

    conf

  • DOI
    10.1109/IWIA.2007.18
  • Filename
    4450642