An asynchronous FIFO with fights: case study in speed optimization

Author

Laberge, Sébastien ; Negulescu, Radu

Author_Institution

Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada

Volume

2

fYear

2000

fDate

2000

Firstpage

755

Abstract

This paper describes an experiment in optimizing digital integrated circuits to maximize operating speeds. The circuit in question is an asynchronous FIFO originally designed for ultra-high-speed. To obtain an even higher throughput, we consider optimizations and local changes of the circuits by using fights, relative delay constraints, and asymmetric and skewed gates. We propose a transistor sizing procedure applicable in these conditions. Part of our procedure is based on the principles of logical effort; in addition, we investigate how to size the circuit with fights. The resulting circuit implemented in TSMC´s 0.35 μm technology can yield throughputs over 1500 millions items per second

Keywords

MOS logic circuits; asynchronous circuits; circuit optimisation; delays; logic gates; 0.35 micron; TSMC; asymmetric gates; asynchronous FIFO; fights; logical effort; operating speeds; relative delay constraints; skewed gates; speed optimization; throughput; transistor sizing procedure; Capacitance; Computer aided software engineering; Constraint optimization; Delay; Digital integrated circuits; Equations; Laboratories; Logic circuits; Microelectronics; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.912987

Filename

912987