DocumentCode
2991253
Title
Delayering of Gate Poly in Stack & Split Gate Memory Structure
Author
Wong, Bridger K S ; Fong, Chan Sieng
Author_Institution
X-FAB Sarawak Sdn. Bhd., Kuching
fYear
2006
fDate
Oct. 29 2006-Dec. 1 2006
Firstpage
418
Lastpage
421
Abstract
The work presented here shows a new technique for removing the gate ploy on top and keeping floating gate (FLGT) below intact in both stack and split gate memory structure. The experiment shows that TMAH solution plus other supporting chemical will be able to provide us a good final sample.
Keywords
digital storage; TMAH solution; floating gate; stack & split gate memory structure; Chemicals; Delay; Dielectric devices; Etching; Hafnium; Lapping; Nonvolatile memory; Plasma applications; Silicon; Split gate flash memory cells;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on
Conference_Location
Kuala Lumpur
Print_ISBN
0-7803-9730-4
Electronic_ISBN
0-7803-9731-2
Type
conf
DOI
10.1109/SMELEC.2006.381094
Filename
4266644
Link To Document