• DocumentCode
    299181
  • Title

    Floorplan area optimization using network analogous approach

  • Author

    Wang, Kai ; Chen, Wai-Kai

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA
  • Volume
    1
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    167
  • Abstract
    In this paper, we propose a new approach to solve a general floorplan area optimization problem. By using the analogy between a floorplan and a resistive network, we have shown that a class of zero wasted area floorplan can be achieved under the shape constraint of continuous aspect ratio. However, in many practical designs, each module may have constraints on its dimensions such as minimum length or width. In this paper, we define the floorplan area minimization problem under the constrained aspect ratio and give necessary conditions for the realization of zero wasted area floorplan under the shape constraints. A set of optimization methods is developed to minimize the wasted area if no zero wasted area floorplan is achievable. Examples are given to demonstrate the approach
  • Keywords
    circuit layout; circuit optimisation; minimisation; analogous network; continuous aspect ratio; design; floorplan area optimization; minimization; modules; resistive network; shape constraint; zero wasted area; Computational complexity; Constraint theory; Microprocessors; Minimization methods; Multiplexing; Resistors; Shape; Thyristors; Topology; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    0-7803-2570-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.1995.521477
  • Filename
    521477