DocumentCode
2991822
Title
MultiChipSat Fault-Tolerant Architecture
Author
McCormack, Matthew M. ; Saenz-Otero, Alvar
Author_Institution
Dept. of Aeronaut. & Astronaut. Eng., Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear
2011
fDate
28-31 March 2011
Firstpage
57
Lastpage
62
Abstract
With the process size of microelectronics shrinking well below 90 nm, the characteristics of upsets experienced by spacecraft avionics are drastically changing; traditional hardware mitigation techniques are reaching performance limitations. A method for achieving reliability, along with the performance capabilities of new technologies, is through the use of an innovative avionics architecture which utilizes both software and hardware redundancy techniques to achieve reliability. Instead of ensuring consistent reliability levels to every operation, the fault mitigation levels are user defined for each operation. Thus the architecture allows the system to be optimized about the needed fault tolerance and performance characteristics of each operation through its use of tightly coupled hardware and software design.
Keywords
aerospace engineering; avionics; fault tolerance; hardware-software codesign; integrated circuits; multiprocessing systems; redundancy; space vehicles; MultiChipSat fault tolerant architecture; avionics architecture; hardware mitigation technique; microelectronics shrinking; redundancy technique; spacecraft avionics; Hardware; Microcontrollers; Program processors; Software reliability; Transistors; Aerospace electronics; fault tolerance; redundancy; reliability engineering;
fLanguage
English
Publisher
ieee
Conference_Titel
Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW), 2011 14th IEEE International Symposium on
Conference_Location
Newport Beach, CA
Print_ISBN
978-1-4577-0303-4
Electronic_ISBN
978-0-7695-4377-2
Type
conf
DOI
10.1109/ISORCW.2011.17
Filename
5753512
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