Stress induced performance degradation in LC oscillators

Stress induced performance degradation in CMOS LC oscillators are investigated systematically. Three architectures of LC oscillators are studied, including NMOS, PMOS, and complementary LC oscillators, for 0.16 μm CMOS technology. The 0.16 μm wafers are stressed, and the aged parameters are extracted. The aged parameters are used to study the stress induced parameter degradations of LC oscillators, including phase noise, amplitude, and the tuning range. After the comparison among the three LC oscillators, it is shown that the complementary LC oscillators are more reliable.