Phase-accumulator based multi-channel high-precision digital PWM architecture

A fully digital accumulator based pulse-width modulation (PWM) architecture operates in frequency domain, permitting to autonomously control frequency and phase parameters independently without the need for additional processor intelligence, e.g. in real-time time-critical applications. The fully digital design is available in text-based hardware design language (HDL), offering flexibility in technology implementation. High-precision sample implementations include 0.35mum CMOS ASIC, CPLD, and FPGA. For clock rates in excess of 100 MHz, pulse step widths of 10 ns and a digital settability of sub-Hertz and fractions of degrees in frequency and phase resolution are realistic. The architecture allows for cascading an in principle unlimited number of synchronous channels rigid in frequency and phase, subject only to available chip or logic resources. Finally, implemented as ASIC, highest clock rates are conceivable either by quartz, or by an on-chip ring oscillator, with the PWM carrier tuned digitally to an external (lower frequency) reference