DocumentCode
2994156
Title
Processor-programmable memory BIST for bus-connected embedded memories
Author
Tsai, Ching-Hong ; Wu, Cheng-Wen
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2001
fDate
2001
Firstpage
325
Lastpage
330
Abstract
We present a processor-programmable built-in self-test (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced
Keywords
application specific integrated circuits; automatic test pattern generation; integrated circuit testing; semiconductor storage; assembly-language program; bus-connected embedded memories; expected outputs; memory outputs; pre-defined test patterns; processor instructions; processor-programmable memory BIST; system-on-a-chip environment; test time; Assembly; Automatic testing; Built-in self-test; Circuit testing; Microprocessors; Random access memory; Signal generators; System testing; System-on-a-chip; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-6633-6
Type
conf
DOI
10.1109/ASPDAC.2001.913327
Filename
913327
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