Performance and power consumption trade-offs for a VLIW DSP

Author

Ibrahim, Mostafa E A ; Rupp, Markus ; Habib, S. E -D

Author_Institution

Inst. of Commun. & RF Eng., Vienna Univ. of Technol., Vienna, Austria

fYear

2009

fDate

9-10 July 2009

Firstpage

1

Lastpage

4

Abstract

Since performance and power consumption optimizations are crucial issues in embedded systems, it is necessary to find a trade-off between these optimization goals. This paper explores the performance and power trade-offs of VLIW processor, specifically the Texas Instruments TMS320C6416T DSP. We evaluate the effect of the global performance optimizations as well as a specific architecture feature on the power consumption of the targeted processor while running typical digital signal and image processing algorithms. We assess the specific C64x+ architecture feature, software pipelined loop (SPLOOP), effect on the power consumption and the performance as well. The binaries used in this study were generated using the Texas Instrument C/C++ Compiler, which allows control over the whole set of optimizations.

Keywords

digital signal processing chips; embedded systems; multiprocessing systems; pipeline processing; power aware computing; program compilers; C64x+ architecture; Texas Instrument C/C++ Compiler; Texas Instruments TMS320C6416T DSP; VLIW DSP; digital signal processing algorithm; embedded systems; image processing algorithm; power consumption optimizations; software pipelined loop; Computer architecture; Digital signal processing; Embedded system; Energy consumption; Image processing; Instruments; Optimization; Signal processing; Software performance; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Circuits and Systems, 2009. ISSCS 2009. International Symposium on

Conference_Location

Iasi

Print_ISBN

978-1-4244-3785-6

Electronic_ISBN

978-1-4244-3786-3

Type

conf

DOI

10.1109/ISSCS.2009.5206135

Filename

5206135