Critical assessment of die level predictor models

The reliability of integrated circuits is becoming of great importance lately as an increasing number of integrated circuits are being used in the automotive sector. As a result, the semiconductor industry is experiencing a greater demand to produce a higher reliability standard of devices without increasing the production cost. There are currently two approaches to increase the reliability of integrated circuits. The first implies new and improved methods of testing. The current reliability testing, which is the Burn-In test, is an expensive process; this provokes the need to further develop and enhance the second approach. The second approach is to predict the lifespan of a device at wafer level. Several prediction models are applied to investigate the correlation between the probe level yield and the burn-in yield. Through this approach, devices which have short lifespan would then be discarded before packaging. There are few prediction models proposed, but those models are static and do not accommodate the variation introduced through the fabrication processes. Though studies have shown that there are correlation between probe level yield and Burn-In yield, the correlation obtained is not significant enough. Therefore, further classification process is applied to wafers having distinct reliability characteristics, before the prediction models are applied. This will in turn optimize the correlation.