On-chip interconnections: impact of adjacent lines on timing

Author

Deschacht ; Servel, G.

Author_Institution

Lab. d´´Inf. de Robotique et de Microelectron., Montpellier, France

fYear

2001

fDate

2001

Firstpage

539

Lastpage

544

Abstract

As CMOS technology scales down, the coupling capacitance between adjacent wires plays dominant part in wire load and interference becomes a serious problem for VLSI design. In this paper, we focus on delay increase caused by adjacent lines. This increase in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. We propose an analytical expression to compute the delay in the presence of coupling that takes explicitly into account interconnect resistance and capacitance, driver resistance and relative driver strengths

Keywords

CMOS integrated circuits; VLSI; capacitance; delays; driver circuits; integrated circuit design; integrated circuit interconnections; timing; wiring; CMOS technology; VLSI design; adjacent lines; adjacent wires; coupling capacitance; deep submicron technologies; delay; delay increase; driver resistance; interconnect capacitance; interconnect resistance; on-chip interconnections; relative driver strengths; timing; wire load; CMOS technology; Capacitance; Delay effects; Delay estimation; Equations; Interference; Switches; Timing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913364

Filename

913364