Application of self-aligned CoSi/sub 2/ interconnection in sub-micron CMOS transistors

Author

Broadbent, Eliot K. ; Irani, Rustom ; Morgan, Alan E.

Author_Institution

Philips Res. Lab., Sunnyvale, CA, USA

fYear

1988

fDate

13-14 June 1988

Firstpage

175

Lastpage

182

Abstract

CoSi/sub 2/ interconnection layers of 0.14-0.40- mu m thickness were applied in a self-aligned manner to 0.75- mu m-gate-length N-channel and P-channel transistors in a complete CMOS device fabrication flow. The sheet resistance above active regions ranged from 1.6 to as low as 0.46 Omega /square for the four CoSi/sub 2/ thickness examined. Using an Al-Cu/TiW metallization, the resistance per contact for 1- mu m-diameter openings to CoSi/sub 2/ was >

Keywords

CMOS integrated circuits; cobalt compounds; contact resistance; insulated gate field effect transistors; integrated circuit technology; metallisation; 0.14 to 0.4 micron; 0.75 micron; AlCu-TiW metallisation; CoSi/sub 2/ selfaligned interconnection; N-channel transistors; P-channel transistors; contact resistance; gain performance; gate length; high-temperature annealing; junction consumption; oxide overlayer; reverse-bias leakage; sheet resistance; silicide formation; submicron CMOS transistors; thickness; Annealing; Contact resistance; Degradation; Fabrication; Gain measurement; Metallization; Performance gain; Planarization; Silicides; Surfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE

Conference_Location

Santa Clara, CA, USA

Type

conf

DOI

10.1109/VMIC.1988.14190

Filename

14190