Exploitation of instruction-level parallelism for optimal loop scheduling

We present a loop scheduling approach which optimally exploits instruction-level parallelism. We develop a flow graph model for the resource constraints allowing a more efficient implementation. The method supports heterogeneous processor architectures and pipelines functional units. Our linear programming implementation produces an optimum loop schedule, making the technique applicable to production compilation and hardware parametrization. Compared to earlier approaches, the approach can provide faster loop schedules and a significant reduction of the problem complexity and solution time.