• DocumentCode
    2997698
  • Title

    Time-constrained loop pipelining

  • Author

    Sanchez, F. ; Cortadella, J.

  • Author_Institution
    Dept. d´Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
  • fYear
    1995
  • fDate
    5-9 Nov. 1995
  • Firstpage
    592
  • Lastpage
    596
  • Abstract
    This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on dividing the problem into two simpler and independent tasks: retiming and scheduling. TCLP explores different sets of resources, searching for a maximum resource utilization. This reduces area requirements. After a minimum set of resources has been found, the execution throughput is increased and the number of registers required by the loop schedule is reduced. TCLP attempts to generate a schedule which minimizes cost in time and area (resources and registers). The results show that TCLP obtains optimal schedules in most cases.
  • Keywords
    parallel algorithms; pipeline processing; processor scheduling; scheduling; TCLP; Time-Constrained Loop Pipelining; loop pipelining; loop schedule; maximum resource utilization; retiming; scheduling; Computer architecture; Costs; Delay effects; Iron; Pipeline processing; Processor scheduling; Registers; Resource management; Throughput; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-8186-8200-0
  • Type

    conf

  • DOI
    10.1109/ICCAD.1995.480177
  • Filename
    480177