DocumentCode
2997701
Title
Testability-preserving circuit transformations
Author
Bryan, M.J. ; Devadas, S. ; Keutzer, K.
Author_Institution
MIT, Cambridge, MA, USA
fYear
1990
fDate
11-15 Nov. 1990
Firstpage
456
Lastpage
459
Abstract
Consideration is given to the synthesis of robustly path-delay-fault testable circuits and it is shown that a single property, ENF reducibility, unifies previous results on robust delay fault testability and multifault testability and proves new ones. The notion of ENF reducibility is used to show that a constrained version of a common area improving transformation, namely, algebraic resubstitution with complement, retains robust path-delay-fault testability. Thus, a more efficient means of synthesizing fully robustly path-delay-fault testable networks is given. The same property of ENF reducibility is used to show that constrained algebraic resubstitution with complement retains multifault irredundancy. Necessary and sufficient conditions are presented for transistor stuck-open fault testability in arbitrary, multilevel networks. It is shown that algebraic factorization, including the constrained use of the complement, can be used to synthesize fully stuck-open fault testable multilevel networks.<>
Keywords
fault location; logic testing; ENF reducibility; algebraic resubstitution; multifault testability; necessary and sufficient conditions; robust path-delay-fault testability; robustly path-delay-fault testable circuits; testability-preserving circuit transformations; transistor stuck-open fault testability; Circuit faults; Circuit synthesis; Circuit testing; Delay; Fabrication; Logic circuits; Logic testing; Network synthesis; Robustness; Sufficient conditions;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2055-2
Type
conf
DOI
10.1109/ICCAD.1990.129952
Filename
129952
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