DocumentCode
2997806
Title
An algorithm for locating logic design errors
Author
Tomita, M. ; Jiang, H.-H. ; Yamamoto, T. ; Hayashi, Y.
Author_Institution
Graduate Sch. of Sci. & Tech., Kobe Univ., Japan
fYear
1990
fDate
11-15 Nov. 1990
Firstpage
468
Lastpage
471
Abstract
Discusses the problem of locating logic design errors, and proposes an algorithm to solve it. Based on the results of logic verification, the authors introduce an input pattern for locating design errors. The pattern contains only one Boolean variable X/X and is used to sensitize the design errors. An algorithm for locating single design errors with the input patterns has been developed. Experimental results have shown the effectiveness of the input patterns and the algorithm for locating single design errors.<>
Keywords
logic CAD; logic testing; Boolean variable; design errors; logic design errors; Algorithm design and analysis; Design engineering; Error correction; Hamming distance; Inverters; Logic circuits; Logic design;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2055-2
Type
conf
DOI
10.1109/ICCAD.1990.129955
Filename
129955
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