DocumentCode
2998512
Title
Delay estimation for technology independent synthesis
Author
Tamiya, Yutaka
Author_Institution
Fujitsu Labs. Ltd., Kawasaki, Japan
fYear
1997
fDate
28-31 Jan 1997
Firstpage
31
Lastpage
36
Abstract
This paper proposes path mapping, a method of delay estimation for technology independent combinational circuits. Path mapping provides fast and accurate delay estimation using the common ideas of tree covering technology mapping. First, path mapping performs technology mapping for all paths in the circuit with minimum delay. Then, it finds the most critical path among all the paths in the circuit. Finally, it answers its path delay as the circuit delay. Experimental results show path mapping estimates more accurate circuit delay than unit delay, and runs much faster than the technology mapper
Keywords
circuit optimisation; combinational circuits; delays; dynamic programming; logic CAD; trees (mathematics); combinational circuit design; critical path; delay estimation; dynamic programming; minimum delay; path mapping; technology independent synthesis; technology mapping; tree covering; unit delay; Circuit synthesis; Combinational circuits; Delay effects; Delay estimation; Design optimization; Equations; Laboratories; Large scale integration; Libraries; Phase measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location
Chiba
Print_ISBN
0-7803-3662-3
Type
conf
DOI
10.1109/ASPDAC.1997.600054
Filename
600054
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