Very Large-Scale Integrated Processor

Many-core processors are designed for improving thread-level parallelism (TLP) across the cores and for keeping instruction-level parallelism (ILP) in each core. However, each application has its own characteristic TLP and ILP. Therefore, a "pre-fabricated" chip multiprocessor (CMP) cannot tolerate a wide range of applications. Recent works attempted to reconfigure the CMP in order to fit the processor to the applications. This paper proposes a scalable processor that is able to up scale and down scale the data path of the adaptive processor. The scaling is based on a chaining interconnection networks between segments. The adaptive processor uses a linear topology to form a stack structure. In order to map the array to a two-dimensional array, a new topology, which we call an S-topology which scales well is also proposed. We assessed costs in terms of area and delay on the S-topology applied to the adaptive processor, and peak performances.