Implementation of a new type DSP PLL using high performance DSP DSSP-1

This paper describes a new digital processing Phase Lock Loop (PLL) implemented on a high performance DSP, the DSSP1. Called the Linear Digital PLL (L-DPLL), the new PLL has linearty in its phase comparison characteristics. It gives fast acquision without increase in jitter, its pull-in range is wider; and its steady state errors and sampling frequency are lower than with conventional PLLs. It also does not require Automatic Gain Control.