Mobility improvement for 45nm node by combination of optimized stress and channel orientation design

Author

Komoda, T. ; Oishi, A. ; Sanuki, T. ; Kasai, K. ; Yoshimura, H. ; Ohno, K. ; Iwai, M. ; Saito, M. ; Matsuoka, F. ; Nagashima, N. ; Noguchi, T.

Author_Institution

Syst. LSI Div. I, Toshiba Corp., Yokohama, Japan

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

217

Lastpage

220

Abstract

Performance improvement of CMOSFET by adopting <100>-channel direction with high tensile stress gate capping layer (GC liner-SiN) was demonstrated. For pMOSFET, higher hole mobility of <100>-channel and lesser short channel effect (SCE) results in 20% improvement of I_on. In addition, this improvement was not sensitive to local uniaxial strain. For nMOSFET, similar to <110>-channel, 10% improvement of I_on is realized in <100>-channel with high tensile stress gate capping layer. Thus, this technology can improve the performance of nMOSFET and pMOSFET without introducing specific additional processes for nMOSFET and pMOSFET.

Keywords

MOSFET; hole mobility; insulating thin films; nanotechnology; semiconductor technology; silicon compounds; tensile strength; 45 nm; <100>-channel direction; CMOSFET; GC liner-SiN; SiN; channel orientation design optimization; high tensile stress gate capping layer; hole mobility improvement; local uniaxial strain; nMOSFET; pMOSFET; performance improvement; short channel effect; stress optimization; CMOS process; CMOS technology; CMOSFETs; Design optimization; Ion implantation; Leakage current; MOSFET circuits; Manufacturing processes; Stress control; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419113

Filename

1419113