DocumentCode
2999874
Title
Research on HDTV decoder synchronization system
Author
Wang, Jingang ; Li, Wei ; Ying Lin ; Wang, Li
Author_Institution
Sch. of Electron. Inf. Eng., Tianjin Univ., China
fYear
2000
fDate
2000
Firstpage
868
Lastpage
870
Abstract
The paper discusses the scheme of HDTV decoder video buffer management, then presents three solutions on decoder system synchronization. Self-adjusting mode is successfully implemented in this HDTV decoder system by FPGA
Keywords
buffer storage; decoding; field programmable gate arrays; high definition television; synchronisation; FPGA; HDTV; decoder synchronization system; self-adjusting mode; system synchronization; video buffer management; Auditory displays; Circuits; Control systems; Decoding; Electronics packaging; Field programmable gate arrays; HDTV; Streaming media; TV; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location
Tianjin
Print_ISBN
0-7803-6253-5
Type
conf
DOI
10.1109/APCCAS.2000.913658
Filename
913658
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