Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chip

We report on a new concept for an easy co-integration, on a same chip, of different MOSFET configurations (GP, LP, HS, buffer transistors) realized after the end of the standard FE process. This poly-gate replacement through contact hole (PRETCH) concept enables replacement of initial poly-silicon gate and/or gate oxide by any gate stack desired. PRETCH addresses multi-Vt control, multi-oxide realization and metal gate integration challenges. As PRETCH gate replacement takes place after PMD (beginning of BE), it is perfectly suitable for high-K integration, allowing low thermal budget (no source and drain anneal seen by HK) and no particular contamination issues. Large potential of PRETCH integration is confirmed by promising morphological results and by very good electrical characteristics of both nMOS and pMOS TiN 90nm gate length MOSFETs. Integration of TiN gate with three different oxide configurations is demonstrated: initial thermal oxide left, replaced by either slot plane antenna [SPA] oxide or high-K. PRETCH concept has also been validated on 3D architectures such as DG. Finally, functional TiN DG inverters and SRAMs are demonstrated.