Transport properties of sub-10-nm planar-bulk-CMOS devices

Transport properties of sub-10-nm planar bulk MOSFETs have been evaluated. Direct-tunneling currents between source and drain (S/D) regions with not only the gate-length effects but also "drain-induced tunneling modulation (DITM)" effects are clearly observed for sub-10-nm CMOS devices at low temperature. Moreover, a quantum mechanical (QM) simulation reveals that the tunneling currents increase with the increase in the temperatures and gate voltages, resulting in the significant contribution to the subthreshold current even at 300 K. Therefore, it is strongly required that the supply-voltage should be reduced, to suppress the DITM effects for the sub-10-nm CMOS devices even under the room-temperature operations.