An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits

This paper shows the impact of I/O pins partitioning on 3D circuits. Previous works on 3D placement did not focused on the I/Os partitioning and placement. This work presents an algorithm based on the logic proximity of the pins, which is used as weights to a min-cut partitioning. Our method calculates the area of the tiers while placing the I/Os on the boundaries. Initial whitespaces and aspect ratio as well as the initial pins orientation and ordering are preserved. The method is compared to two other simplistic methods for pins partitioning. Our experimental results show that our method is efficient since it can balance the I/O pins distribution in the various tiers while leading to improvements in wire length and number of 3D vias.