Macrocell placement with temperature profile optimization

With the dramatic increase of power consumption by modern high-performance circuits, cross-chip temperature differentials as large as 10~20 degrees have been commonly observed. It is thus imperative to address the thermal issue as early in the design process as possible, to avoid the associated performance and reliability problems. In this paper we present a temperature sensitive macro cell placement tool aiming at improving the quality of the temperature distribution of a circuit design. Our placement tool uses the concept of transfer thermal resistance and the principle of superposition to calculate the optimal power and temperature distributions under the given power budget and boundary conditions, and to efficiently update incremental temperature profile changes during the placement process. The tool has been tested with several benchmark circuits. Simulation results show good compatibility with conventional physical design constraints, with noticeable improvements on the final temperature profile and very little area increase