Multistage Interconnection Network for MPSoC: Performances study and prototyping on FPGA

Author

Neji, B. ; Aydi, Y. ; Ben-atitallah, R. ; Meftaly, S. ; Abid, M. ; Dykeyser, J.-L.

Author_Institution

Nat. Eng. Sch. of Sfax, CES, Sfax

fYear

2008

fDate

20-22 Dec. 2008

Firstpage

11

Lastpage

16

Abstract

Multiprocessor system on chip is a concept that aims to integrate multiple hardware and software in a chip. multistage interconnection network is considered as a promising solution for applications which use parallel architectures integrating a large number of processors and memories. in this paper, we present a model of multistage interconnection network and a design of prototyping on FPGA. This enabled the comparison of the proposed model with the full crossbar network, and the estimation of performance in terms of area, latency and energy consumption. The Multistage Interconnection Networks are well adapted to MPSoC architecture. They meet the needs of intensive signal processing and they are scalable to connect a large number of modules.

Keywords

field programmable gate arrays; multiprocessor interconnection networks; system-on-chip; FPGA; MPSoC; integrate multiple hardware; integrate multiple software; multiprocessor system on chip; multistage interconnection network; Application software; Field programmable gate arrays; Hardware; Multiprocessing systems; Multiprocessor interconnection networks; Network-on-a-chip; Parallel architectures; Prototypes; Software prototyping; System-on-a-chip; FPGA; MIN; MPSoC; NoC;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Workshop, 2008. IDT 2008. 3rd International

Conference_Location

Monastir

Print_ISBN

978-1-4244-3479-4

Electronic_ISBN

978-1-4244-3478-7

Type

conf

DOI

10.1109/IDT.2008.4802456

Filename

4802456