SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells

Author

Monfray, S. ; Chanemougame, D. ; Bore, S. ; Talbot, A. ; Leverd, F. ; Planes, N. ; Delille, D. ; Dutartre, D. ; Palla, R. ; Morand, Y. ; Descombes, S. ; Samson, M.P. ; Vulliet, N. ; Sparks, T. ; Vandooren, A. ; Skotnicki, T.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

635

Lastpage

638

Abstract

In this paper, we demonstrate for the first time full integration of highly performant NMOS and PMOS silicon-on-nothing (SON) devices into circuits. We demonstrated fully functional SRAMs cells with very good yield, showing static noise margin (SNM) of 175mV and write margin (WM, stable "read 0") above 500mV. The optimized SON devices show performance for NMOS and for PMOS that is among the best published data (with drive current up to 1100/350μA/μm for 138/20nA/μm I_off for NMOS and PMOS devices respectively @V_dd=1.2V, I_ox=16A). Finally, we present also the implementation of the SON process into a new "localized SOI" architecture on bulk. This new and simplified SON process is also demonstrated by fully operational SRAM cells.

Keywords

MOS integrated circuits; SRAM chips; elemental semiconductors; silicon; silicon-on-insulator; 1.2 V; 16 A; 175 mV; NMOS silicon-on-nothing devices; PMOS silicon-on-nothing devices; SON device optimization; Si; drive current; fully functional SRAM cells; fully operational SRAM cells; localized SOI architecture; silicon-on-nothing technological CMOS platform; static noise margin; write margin; Acceleration; CMOS technology; Circuit noise; MOS devices; Morphology; Random access memory; Reproducibility of results; Semiconductor device noise; Thickness control; Thin film devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419246

Filename

1419246