Chip-level electromigration measurement technique for multi-segmented interconnect test structures

Author

Zamani, Nasser ; Dhiman, Jaipal ; Buehler, Martin

Author_Institution

Jet Propulsion Lab., Pasadena, CA, USA

fYear

1989

fDate

12-13 Jun 1989

Firstpage

198

Lastpage

207

Abstract

Electromigration life testing of multisegment test structures involves the measurement and analysis of space- and time-variant stress temperature distributions. A technique using the concept of a thermal coupling matrix was developed which allows an accurate (⩽0.5°C) determination of each metal segment temperature during stress test. In the data analysis, each segment failure time is adjusted to the target stress temperature. This results in more accurate values for the calculated electromigration parameters

Keywords

electromigration; failure analysis; integrated circuit testing; life testing; metallisation; temperature distribution; IC metallisation; MUSIC structure; chip level electromigration measurement; electromigration life testing; multi-segmented interconnect test structures; segment failure time; stress temperature distributions; thermal coupling matrix; Condition monitoring; Electromigration; Life testing; Measurement techniques; Multiple signal classification; Probes; Switches; Temperature; Thermal resistance; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1989.78023

Filename

78023