Integration of manufacturable 65nm-node HfSiON transistors optimized with low-thermal-budget CMOS process

Author

Mineji, A. ; Tamura, Y. ; Watanabe, T. ; Ozaki, H. ; Ootsuka, F. ; Aoyama, T. ; Shibata, K. ; Tsujita, K. ; Ohashi, N. ; Yasuhira, M. ; Arikado, T.

Author_Institution

Semicond. Leading Edge Technol. Inc., Ibaraki, Japan

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

927

Lastpage

930

Abstract

This paper describes the 65nm-node HfSiON transistors that have been fully integrated to SRAM array. By optimizing the thermal process after the gate stack formation, the scaling of EOT has been attained without introducing additional high-k formation techniques. Highly manufacturable HfSiON transistors with the symmetrical Vth values suitable for SRAM operation at 1.1V power supply are demonstrated.

Keywords

CMOS memory circuits; MOSFET; SRAM chips; hafnium compounds; optimisation; silicon compounds; CMOS process; HfSiON; HfSiON transistors; SRAM array; gate stack formation; high-k formation techniques; thermal process; Annealing; CMOS process; Crystallization; Gate leakage; High K dielectric materials; Leakage current; Manufacturing processes; Random access memory; Silicon compounds; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419334

Filename

1419334

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3004804