• DocumentCode
    3006123
  • Title

    Advanced single-chip signal processor

  • Author

    Nishitani, T. ; Kuroda, L. ; Kawakami, Y. ; Tanaka, H. ; Nukiyama, T.

  • Author_Institution
    NEC Corporation, Kawasaki, Japan
  • Volume
    11
  • fYear
    1986
  • fDate
    31503
  • Firstpage
    409
  • Lastpage
    412
  • Abstract
    A CMOS single chip signal processor, which has 32-bit floating point arithmetic units and large capacity on-chip memories, has been developed. The processor, having a floating point parallel multiplier, a floating point accumulator, two 512- word data RAMs, a 1024-word data ROM and a 2048- word program ROM, is implemented within a 15.4 × 8.4 mm chip area, containing 370,000 elements. As the processor is designed to perform highly accurate multiply-accumulate operations for digital filtering and to attain complex addressing capability for FFT computation, this processor can execute FIR computation at the 150 nsec per tap rate, as well as achieve 1024 point complex FFT computation in 12.3 msec.
  • Keywords
    CMOS process; Digital filters; Filtering; Finite impulse response filter; Floating-point arithmetic; High performance computing; Process design; Random access memory; Read only memory; Signal processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
  • Type

    conf

  • DOI
    10.1109/ICASSP.1986.1169046
  • Filename
    1169046