DocumentCode
3006279
Title
VLSI processor design of real-time data compression for high-resolution imaging radar
Author
Fang, Wai-Chi
Author_Institution
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
fYear
1994
fDate
19-23 Sep 1994
Firstpage
441
Lastpage
444
Abstract
For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems
Keywords
CMOS digital integrated circuits; VLSI; adaptive signal processing; application specific integrated circuits; data compression; digital signal processing chips; radar computing; radar imaging; real-time systems; synthetic aperture radar; DSP chip; SAR data; VLSI processor design; block adaptive quantizer algorithm; high-resolution imaging radar; real-time data compression; Computer buffers; Data compression; High-resolution imaging; Image resolution; Process design; Quantization; Radar imaging; Real time systems; Synthetic aperture radar; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-2020-4
Type
conf
DOI
10.1109/ASIC.1994.404524
Filename
404524
Link To Document