DocumentCode
3006617
Title
A single-chip RSA processor implemented in a 0.5 μm rule gate array
Author
Ishii, Shinji ; Ohyama, Katsuichi ; Yamanaka, Kiyoshi
Author_Institution
NTT Human Interface Labs., Kanagawa, Japan
fYear
1994
fDate
19-23 Sep 1994
Firstpage
433
Lastpage
436
Abstract
A prototype single-chip modular exponentiation LSI is implemented, which is capable of high-speed RSA public-key encryption processing, in a 0.5 μm-rule gate array. With this LSI, computation can be done using key arbitrary lengths of up to 1024 bits, and a throughput of 10 kbps can be achieved. This paper describes the technical aspects of the LSI´s design and performance
Keywords
CMOS logic circuits; cryptography; large scale integration; logic arrays; public key cryptography; 0.5 micron; 10 kbit/s; 1024 bit; arbitrary lengths; gate array; modular exponentiation LSI; public-key encryption processing; single-chip RSA processor; technical aspects; throughput; Electronics industry; Hardware; Humans; Laboratories; Large scale integration; Prototypes; Public key; Public key cryptography; Telecommunication computing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-2020-4
Type
conf
DOI
10.1109/ASIC.1994.404526
Filename
404526
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