Steady-State Analysis of Power Factor Correctors with a Fast Output-Voltage Feedback Loop

When a power factor corrector (PFC) is designed with a fast output-voltage feedback loop, the study of the power stage varies in comparison with the one carried out with a slow output-voltage feedback loop. This is a consequence of the voltage ripple that appears in the control signal. The static behaviour of a PFC with a fast output-voltage feedback loop is studied in this paper using two parameters: the module of the relative voltage ripple on the control signal and its phase angle. The total power processed by the PFC depends on these parameters, which do not change with the load and which determine the Total harmonic distortion (THD) and the power factor (PF) at the input of the PFC. Furthermore, these parameters also determine the maximum power that can be processed by the converter while still complying with EN 61000 -3 - 2 regulations for class A and class B equipment. When the converter must comply with the aforementioned regulations for class C or class D equipment, however, the compliance does not depend on the power processed by the PFC and not all the possible combinations of the relative ripple of the control signal and of its phase angle manage to comply with these regulations. As regards the bulk capacitor, its value for a given value of the output voltage ripple is also a function of both the aforementioned parameters. Finally, the study was verified by simulation and in a prototype.