DocumentCode
3008051
Title
Molded chip scale package for high pin count
Author
Baba, Shinji ; Tomita, Yoshihiro ; Matsuo, Mitsuyasu ; Matsushima, Hironori ; Ueda, Naoto ; Nakagawa, Osamu
Author_Institution
IC Assembly Eng. Dept., Mitsubishi Electr. Corp., Hyogo, Japan
fYear
1996
fDate
28-31 May 1996
Firstpage
1251
Lastpage
1257
Abstract
A unique molded Chip Scale Package (CSP) associated 1024 pin counts has been developed. The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and moisture induced crack resistivity. Finally, enhanced electrical and thermal characteristics were calculated
Keywords
integrated circuit packaging; cost competitiveness; electrical characteristic; high mount density; high pin count; moisture induced crack resistivity; molded chip scale package; reliability testing; thermal characteristics; thermal cycling; Chip scale packaging; Conductivity; Cost function; Design optimization; Electric variables; Moisture; Performance evaluation; Process design; Testing; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 1996. Proceedings., 46th
Conference_Location
Orlando, FL
ISSN
0569-5503
Print_ISBN
0-7803-3286-5
Type
conf
DOI
10.1109/ECTC.1996.550895
Filename
550895
Link To Document