Prep benchmarks reveal performance and capacity tradeoffs of programmable logic devices

Author

Kliman, Stephen

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

376

Lastpage

382

Abstract

The process of choosing a programmable logic device (PLD) involves reviewing marketing material, studying specifications and learning PLD development tools. Until benchmark circuits were developed by the Programmable Electronics Performance Corporation (PREP), this was a costly and timely undertaking because no standard existed to compare PLDs against one another. This paper analyzes the PREP benchmark results and shows the capacity and performance tradeoffs associated with different programmable logic devices

Keywords

application specific integrated circuits; logic design; programmable logic devices; ASIC; PLD development tools; PREP benchmark results; Programmable Electronics Performance Corporation; benchmark circuits; capacity tradeoffs; logic functions; logic module; performance tradeoffs; programmable logic devices; Application specific integrated circuits; Counting circuits; Decoding; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Programmable logic arrays; Programmable logic devices; Prototypes; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404537

Filename

404537