Hardware efficient recursive VLSI architecture for multilevel lifting 2-D DWT

In this paper, we present a recursive hardware efficient multilevel lifting 2-D Discrete wavelet transform (DWT) based on dual scan architecture (DSA). Proposed pipelined architecture can be used for any image size with a little modification in length of line buffers. In recent years multilevel DWT is utilized in many applications because of good energy compaction in higher level DWT coefficients. The control path is defined in a manner that the interleaved clock cycles are efficiently utilized to get multilevel DWT coefficients. The proposed scanning technique enables the column processor to process with minimum latency. The actual computation time (ACT) required is only N²/2 with additional latency of just three clock cycles for first level, where N is the width of the image. Latency of proposed architecture to compute the j level coefficients is 2=3(4^j − 1). Proposed design uses two line buffers with N/2 size along with a multiplexer for interleaving operations to compute multilevel DWT. Proposed scheme for multilevel architecture can be used for both lifting (5,3) and (9,7) filters with modification in only 2-D DSA block.