DocumentCode
3012446
Title
SOI-DRAM circuit technologies for low power high speed multi-giga scale memories
Author
Kuge, S. ; Tsuruda, T. ; Tomishima, S. ; Tsukude, M. ; Yamagata, T. ; Arimoto, K.
Author_Institution
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
fYear
1995
fDate
8-10 June 1995
Firstpage
103
Lastpage
104
Abstract
New SOI-DRAM circuits were proposed and described. The body bias controlling technique, especially super body-synchronous sensing, is found to be suitable for low voltage operation. A new type of redundancy enables Icc2 reduction and promises high yield against the increasing standby current failure.
Keywords
DRAM chips; redundancy; silicon-on-insulator; Icc2 reduction; SOI DRAM circuit technologies; Si; body bias controlling technique; dynamic RAM; high speed operation; low power operation; low voltage operation; multi-giga scale memories; redundancy; standby current failure; super body-synchronous sensing; Capacitance; Integrated circuit technology; Laboratories; Low voltage; P-n junctions; Random access memory; Subthreshold current; Threshold voltage; Ultra large scale integration; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7800-2599-0
Type
conf
DOI
10.1109/VLSIC.1995.520706
Filename
520706
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