Analysis and Design of a 14-bit SAR ADC using self-calibration DAC

This paper presents the analysis of a calibration technique for high-resolution successive-approximation register analog-to-digital converter (SAR ADC) using a calibration digital-to-analog converter (DAC), which simplifies the complicated relationships among various design parameters and provides design insight that aids in parameter selection. Based on this analysis, an energy-efficient, 14-bit resolution SAR ADC is realized in a 0.18µm CMOS technology. The relationships among the following factors are analyzed in details: (1) the main DAC resolution, (2) the calibration accuracy, (3) the capacitor value to be calibrated, and (4) the parasitic capacitors. Post-layout simulation results are presented and specifically Monte Carlo (MC) shows promising result that is in agreement with the proposed calibration technique.