FPGA implementation analysis of polyphase channelizer performing sample rate change required for both matched filtering and channel frequency spacing

The paper presents the architectural domain analysis for FPGA (Field Programmable Gate Array) implementation of a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine that performs two different re-sampling tasks required for spectral shaping and for M-channel channelizer. In terms of algorithms; Radix-2 FFT, Prime Factor and Winograd Fourier Transform are considered for IFFT, where as the polyphase filter is analyzed in terms of symmetric structure, and serial polyphase structures with serial and parallel MAC approaches. The computational workload for these algorithms and their implementation structures are presented together with their hardware mapping to a Virtex-5 FPGA by exploiting the inherent parallelism. Their resource utilizations and Design Space Exploration in terms of Area-Time is presented along with different optimization techniques.