Elimination of metal bridging failure in VLSI metallization and yield enhancement of FLAT ROM device

Author

Younan, Hua

Author_Institution

Chartered Semicond. Manuf. Ltd., Singapore

fYear

1998

fDate

1998

Firstpage

17

Lastpage

19

Abstract

A few lots of wafers (FLAT ROM) were reported with low yield (5-20%) issue. RIE, SEM and EDX techniques were used to identify the root causes. Al metal filaments were found at particular locations, which had resulted in metal bridging failure. They were found to be due to the narrow space between the two polysilicon layers and insufficient metal etching. The solution to eliminate these metal filaments is to increase overetch of L90 from 100 to 135 or change the space between the two poly layers. After using a new overetch recipe (135), the wafer sort yield was greatly enhanced

Keywords

VLSI; X-ray chemical analysis; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; integrated circuit yield; integrated memory circuits; read-only storage; scanning electron microscopy; sputter etching; Al; Al metal filaments; EDX; FLAT ROM device; RIE; SEM; Si; VLSI metallization; failure root causes; metal bridging failure; metal etching; metal filaments; overetch; polysilicon layer spacing; wafer lots; wafer sort yield; wafer yield; yield enhancement; Etching; Failure analysis; Gases; Inspection; Metallization; Passivation; Read only memory; Surface contamination; Topology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 1998. Proceedings. ICSE '98. 1998 IEEE International Conference on

Conference_Location

Bangi

Print_ISBN

0-7803-4971-7

Type

conf

DOI

10.1109/SMELEC.1998.781142

Filename

781142