A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line

A fast-lock-in harmonic-free all-digital delay-locked-loop (ADDLL) in STMicro 32nm CMOS technology is presented. The ADDLL uses a novel complementary delay line with lattice-type delay elements. The complementary line can effectively reduce at most 50% active delay elements than a single line. Less active delay elements make better suppression of supply-induced jitter. The lattice-type delay element is beneficial to high frequency applications because of its small intrinsic delay. The ADDLL employs a 9-bit configurable SAR controller to achieve fast lock. Moreover, it can work in a wide-range application (200MHz ∼ 2GHz) without the harmonic-lock problem of conventional SAR controllers. Under a 1.1V power supply, the ADDLL has a delay resolution of 8 ps and the lock time is 36 cycles at 200 MHz and 24 cycles at 2GHz.