Modeling of UHF voltage multiplier for radio-triggered wake-up circuit

An analytical model of an ultra-high frequency (UHF) voltage multiplier for the radio-triggered wake-up circuit is derived in this paper. The model is compliant with HSpice circuit simulations, and it allows for short design time of an optimal voltage multiplier. With low incident RF signal power, the optimal design of the voltage multiplier takes into account the number of stages of the multiplier, the diode saturation current and the emission coefficient, and the load impedance. We design and optimize a voltage multiplier with a matching depletion layer capacitance according to this model. With an RF input signal of 2.4 GHz and 200 nW, it can provide a constant DC output of 1 V within tens of microsecond.